Large quantities of read-only memory (ROM) are required in deep submicron technology, i.e., 32 nm technology, System on a Chip (SoC) designs. However, as the size of technology is reduced, it becomes more difficult to manufacture chips with sufficient ROM without defects. Accordingly, the ability to repair ROM bit failures is required to produce chips with sufficient ROM. But, ROM redundancy introduces challenges not encountered with random-access memory (RAM) redundancy. More specifically, redundant elements in the ROM are loaded with specific data contents of the segment of the array being replaced. This is accomplished by replacing an entire word in the address space which requires routing the entire data width of the ROM. Replacing an entire word requires more data routing than repairing a failed bit.
To determine if a bit has failed, ROM built-in-self-test (BIST) techniques sum the data read sequentially from the address space into a multiple input signature register (MISR), and compare the resultant signature to the expected signature for array contents in a single “Go/No-Go” comparison. However, the ROM BIST does not identify the address of the failing bit. Instead, an external diagnostic tester is used to identify the failing address and the data positions which require repair, which is then coded into programmable memory elements. That is, ROM BIST reads the ROM and compresses the content into the MISR, which is compared to the expected MISR value to determine whether the bit value is incorrect. However, the ROM BIST does not determine the location of a failed bit without the assistance of a diagnostic tester.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.